`include "defines.v"
`define  BEQ      32'b?????????????????000?????1100011
`define  BNE      32'b?????????????????001?????1100011
`define  BLT      32'b?????????????????100?????1100011
`define  BGE      32'b?????????????????101?????1100011
`define  BLTU     32'b?????????????????110?????1100011
`define  BGEU     32'b?????????????????111?????1100011
`define  JALR     32'b?????????????????000?????1100111
`define  JAL      32'b?????????????????????????1101111
`define  LUI      32'b?????????????????????????0110111
`define  AUIPC    32'b?????????????????????????0010111
`define  ADDI     32'b?????????????????000?????0010011
`define  SLLI     32'b000000???????????001?????0010011
`define  SLTI     32'b?????????????????010?????0010011
`define  SLTIU    32'b?????????????????011?????0010011
`define  XORI     32'b?????????????????100?????0010011
`define  SRLI     32'b000000???????????101?????0010011
`define  SRAI     32'b010000???????????101?????0010011
`define  ORI      32'b?????????????????110?????0010011
`define  ANDI     32'b?????????????????111?????0010011
`define  ADD      32'b0000000??????????000?????0110011
`define  SUB      32'b0100000??????????000?????0110011
`define  SLL      32'b0000000??????????001?????0110011
`define  SLT      32'b0000000??????????010?????0110011
`define  SLTU     32'b0000000??????????011?????0110011
`define  XOR      32'b0000000??????????100?????0110011
`define  SRL      32'b0000000??????????101?????0110011
`define  SRA      32'b0100000??????????101?????0110011
`define  OR       32'b0000000??????????110?????0110011
`define  AND      32'b0000000??????????111?????0110011
`define  ADDIW    32'b?????????????????000?????0011011
`define  SLLIW    32'b0000000??????????001?????0011011
`define  SRLIW    32'b0000000??????????101?????0011011
`define  SRAIW    32'b0100000??????????101?????0011011
`define  ADDW     32'b0000000??????????000?????0111011
`define  SUBW     32'b0100000??????????000?????0111011
`define  SLLW     32'b0000000??????????001?????0111011
`define  SRLW     32'b0000000??????????101?????0111011
`define  SRAW     32'b0100000??????????101?????0111011
`define  LB       32'b?????????????????000?????0000011
`define  LH       32'b?????????????????001?????0000011
`define  LW       32'b?????????????????010?????0000011
`define  LD       32'b?????????????????011?????0000011
`define  LBU      32'b?????????????????100?????0000011
`define  LHU      32'b?????????????????101?????0000011
`define  LWU      32'b?????????????????110?????0000011
`define  SB       32'b?????????????????000?????0100011
`define  SH       32'b?????????????????001?????0100011
`define  SW       32'b?????????????????010?????0100011
`define  SD       32'b?????????????????011?????0100011
`define  FENCE    32'b?????????????????000?????0001111
`define  FENCE_I  32'b?????????????????001?????0001111
`define  ECALL    32'b00000000000000000000000001110011
`define  CSRRW    32'b?????????????????001?????1110011
`define  CSRRS    32'b?????????????????010?????1110011
`define  CSRRC    32'b?????????????????011?????1110011
`define  CSRRWI   32'b?????????????????101?????1110011
`define  CSRRSI   32'b?????????????????110?????1110011
`define  CSRRCI   32'b?????????????????111?????1110011
`define  TRAP     32'b00000000000000000000000001101011
`define  PUTCH    32'b00000000000000000000000001111011
`define  MRET     32'b00110000001000000000000001110011
`define  NOP      32'b00000000000000000000000000010011

// def MUL                = BitPat("b0000001??????????000?????0110011")
// def MULH               = BitPat("b0000001??????????001?????0110011")
// def MULHSU             = BitPat("b0000001??????????010?????0110011")
// def MULHU              = BitPat("b0000001??????????011?????0110011")
// def DIV                = BitPat("b0000001??????????100?????0110011")
// def DIVU               = BitPat("b0000001??????????101?????0110011")
// def REM                = BitPat("b0000001??????????110?????0110011")
// def REMU               = BitPat("b0000001??????????111?????0110011")
// def MULW               = BitPat("b0000001??????????000?????0111011")
// def DIVW               = BitPat("b0000001??????????100?????0111011")
// def DIVUW              = BitPat("b0000001??????????101?????0111011")
// def REMW               = BitPat("b0000001??????????110?????0111011")
// def REMUW              = BitPat("b0000001??????????111?????0111011")
// def LR_W               = BitPat("b00010??00000?????010?????0101111")
// def SC_W               = BitPat("b00011????????????010?????0101111")
// def LR_D               = BitPat("b00010??00000?????011?????0101111")
// def SC_D               = BitPat("b00011????????????011?????0101111")
// def EBREAK             = BitPat("b00000000000100000000000001110011")
// def URET               = BitPat("b00000000001000000000000001110011")
// def DRET               = BitPat("b01111011001000000000000001110011")
// def SFENCE_VMA         = BitPat("b0001001??????????000000001110011")
// def WFI                = BitPat("b00010000010100000000000001110011")
// def CUSTOM0            = BitPat("b?????????????????000?????0001011")
// def CUSTOM0_RS1        = BitPat("b?????????????????010?????0001011")
// def CUSTOM0_RS1_RS2    = BitPat("b?????????????????011?????0001011")
// def CUSTOM0_RD         = BitPat("b?????????????????100?????0001011")
// def CUSTOM0_RD_RS1     = BitPat("b?????????????????110?????0001011")
// def CUSTOM0_RD_RS1_RS2 = BitPat("b?????????????????111?????0001011")
// def CUSTOM1            = BitPat("b?????????????????000?????0101011")
// def CUSTOM1_RS1        = BitPat("b?????????????????010?????0101011")
// def CUSTOM1_RS1_RS2    = BitPat("b?????????????????011?????0101011")
// def CUSTOM1_RD         = BitPat("b?????????????????100?????0101011")
// def CUSTOM1_RD_RS1     = BitPat("b?????????????????110?????0101011")
// def CUSTOM1_RD_RS1_RS2 = BitPat("b?????????????????111?????0101011")
// def CUSTOM2            = BitPat("b?????????????????000?????1011011")
// def CUSTOM2_RS1        = BitPat("b?????????????????010?????1011011")
// def CUSTOM2_RS1_RS2    = BitPat("b?????????????????011?????1011011")
// def CUSTOM2_RD         = BitPat("b?????????????????100?????1011011")
// def CUSTOM2_RD_RS1     = BitPat("b?????????????????110?????1011011")
// def CUSTOM2_RD_RS1_RS2 = BitPat("b?????????????????111?????1011011")
// def CUSTOM3            = BitPat("b?????????????????000?????1111011")
// def CUSTOM3_RS1        = BitPat("b?????????????????010?????1111011")
// def CUSTOM3_RS1_RS2    = BitPat("b?????????????????011?????1111011")
// def CUSTOM3_RD         = BitPat("b?????????????????100?????1111011")
// def CUSTOM3_RD_RS1     = BitPat("b?????????????????110?????1111011")
// def CUSTOM3_RD_RS1_RS2 = BitPat("b?????????????????111?????1111011")
// def SLLI_RV32          = BitPat("b0000000??????????001?????0010011")
// def SRLI_RV32          = BitPat("b0000000??????????101?????0010011")
// def SRAI_RV32          = BitPat("b0100000??????????101?????0010011")
// def RDCYCLE            = BitPat("b11000000000000000010?????1110011")
// def RDTIME             = BitPat("b11000000000100000010?????1110011")
// def RDINSTRET          = BitPat("b11000000001000000010?????1110011")
// def RDCYCLEH           = BitPat("b11001000000000000010?????1110011")
// def RDTIMEH            = BitPat("b11001000000100000010?????1110011")
// def RDINSTRETH         = BitPat("b11001000001000000010?????1110011")

`define CSR_ADDR_mstatus    12'h300
`define CSR_ADDR_misa       12'h301
`define CSR_ADDR_medeleg    12'h302
`define CSR_ADDR_mideleg    12'h303
`define CSR_ADDR_mie        12'h304
`define CSR_ADDR_mtvec      12'h305
`define CSR_ADDR_mscratch   12'h340
`define CSR_ADDR_mepc       12'h341
`define CSR_ADDR_mcause     12'h342
`define CSR_ADDR_mtval      12'h343
`define CSR_ADDR_mip        12'h344
`define CSR_ADDR_mcycle     12'hb00
`define CSR_ADDR_minstret   12'hb02
`define CSR_ADDR_mvendorid  12'hf11
`define CSR_ADDR_marchid    12'hf12
`define CSR_ADDR_mimpid     12'hf13
`define CSR_ADDR_mhartid    12'hf14

`define Cause_misaligned_fetch    63'h0
`define Cause_fetch_access        63'h1
`define Cause_illegal_instruction 63'h2
`define Cause_breakpoint          63'h3
`define Cause_misaligned_load     63'h4
`define Cause_load_access         63'h5
`define Cause_misaligned_store    63'h6
`define Cause_store_access        63'h7
`define Cause_user_ecall          63'h8
`define Cause_machine_ecall       63'hb
`define Cause_clint               63'h7

`define Cause_extInterrupt        63'd11